FIG. 1A depicts an Unified Memory Architecture (UMA) for processing graphics to display on a liquid crystal display (LCD) panel 130. A central processing unit (CPU) 110 is coupled to a chipset 120. The chipset 120 comprises a main memory 122 and a memory controller hub (MCH) 124. The MCH 124 is the central hub for processing data. The MCH is also coupled to a graphics engine 126 and a display controller 128. The CPU 110 determines what data is to be displayed. Data that is to be displayed is accessed from main memory 122 by the MCH 124.
Data is stored in main memory 122 in packet format. The packet comprises a header portion and a payload portion. The header provides the position and dimension of the image to be displayed. The payload contains the data of the image to be displayed. Thus, the packet graphics files must be rasterized or reconstructed out of those components before they can be presented as an actual image on the panel 130. The graphics engine 126 computes and creates a bitmap of the data accessed by the MCH 124. The bitmapped file contains pixel image data. Each dot on the LCD panel 130 is represented by data in the bitmapped file. The display controller 128 sends the data stream of pixels to a panel 130 to be displayed.
FIG. 1B depicts a Discrete Graphics Architecture (DGA) for processing graphics to display on a LCD 170. For this system, a CPU 140 is coupled to a chipset 150. The chipset 150 comprises a main memory 152 and a MCH 154. The MCH 154 is the central hub for processing data. In contrast to the system of FIG. 1A, graphics engine 162 and display controller 164 are located on a discrete graphics chip 160 rather than on the chipset 150. In addition, the discrete graphics chip 160 comprises a local frame buffer 166 for graphics engine 162. The data that is to be displayed on LCD 170 is obtained from the frame buffer 166 rather than main memory 152.
When the system is idle in the UMA, the CPU 110 and the MCH 124 may not quiesce to the lowest power state because the circuits have to maintain the data display stream to the LCD panel 130. A computer system may be in an idle state when no data is being entered into the computer and when no programs are running. An user input such as a mouse-click or a key stroke brings the CPU 110 out of idle. The DGA of FIG. 1B may be more efficient than the UMA because the UMA drives data from a large main memory 152 to the LCD 170 while the DGA drives a smaller, dedicated, and less shallow memory subsystem to the LCD 170. The CPU 140 and the MCH 124 of the DGA, however, also do not quiesce when the system is idle. In both the UMA and the DGA, an image frame is periodically transferred to the LCD panels 130 and 170, regardless if the new frame is different from the previous frame.